1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a device which includes a capacitor.
2. Description of the Related Art
Dynamic random access memories (DRAMs) with memory cells consisting of a single transistor and a capacitor are known. As is also known in relation to DRAMs, data is stored as charge accumulation in the cell capacitor. With attempts to increase the integration level and thus the packing density of such memories comes the problem of maintaining sufficient charge accumulation in the cell capacitor. One attempted solution involves providing the cell capacitor with a dielectric film having a high dielectric constant.
An example of a conventional semiconductor memory device with a capacitor, and of a process by which it can be formed is illustrated in FIGS. 10a to 10f.
As illustrated in FIG. 10a, there is provided a p-type silicon substrate on which are formed a field oxide film 2 and gate oxide film 3. The field oxide and gate oxide may be formed using conventional selective oxidation techniques. Gate electrodes 4 are provided for connection to word lines (not shown). N-type diffusion layers 5 are formed as source and drain regions of the memory cell transistor.
As illustrated in FIG. 10b, an interlayer insulating film 6-1 is formed and then selectively etched to open a first contact hole 15-1. Referring to FIG. 10c, a first conductor layer 7-1, which may be a polysilicon layer, is formed over the upper layer of the device being formed. The first conductor layer 7-1 is selectively etched (FIG. 10d) to form a lower electrode. A dielectric film 12 having a high dielectric constant is then formed. The high-dielectric-constant film 12 is formed, for example, by sputtering SrTiO.sub.3 or the like, or by the anodicoxidation of tantalum.
As illustrated in FIG. 10e, a second conductor layer 7-2 is formed and selectively etched to form an upper electrode. Thus lower and upper electrodes 7-1, 7-2, respectively, and dielectric film 12 constitute a capacitor element. Interlayer insulating film 6-3 is formed and selectively etched to open a second contact hole 15-2 (FIG. 10f). A conductor layer 7-3 is then formed as a bit line connected to the source or drain region of the cell transistor. Thus, a memory cell is fabricated.
A disadvantage of the above described prior art memory cell is that the sputtering of SrTiO.sub.3 or the like or the anodicoxidation of tantalum causes the surface of the first conductor layer 7-1, when made of polysilicon, to oxidize to a silicon oxide film of a low dielectric constant, resulting in a cell capacitor having a small storage capacitance. In addition, the formation of the high-dielectric-constant film 12 over the entire surface, as described above, causes an increase in parasitic capacitance, due to the existence of the film 12 (represented by a circle A in FIG. 10f) between lower electrodes of adjacent memory cell capacitors, and similarly an increase in parasitic capacitance due to the existence of the film 12 (represented by a circle B in FIG. 10f) between word line 4' connected to a gate electrode of an adjacent memory cell transistor and a bit line consisting of a third conductor layer 7-3.
U.S. Pat No. 4,982,309 discloses an electrical ceramic oxide device. A ruthenium oxide film is used as a lower electrode of the device. An electrical ceramic oxide dielectric material is deposited over the body of the lower electrode. Such a device exhibits a parasitic capacitance problem similar to that described above.